
`include "defines.v"

module mux_alu_ia (
    input  wire              rst,
    
    input  wire [`BUS_WIDTH] inst_addr,
    input  wire [`BUS_WIDTH] r_data1,
    input  wire              alu_asrc,

    output reg  [`BUS_WIDTH] alu_ia
);


    always @(*) begin
        if (rst) begin
            alu_ia = `ZERO_WORD;
        end
        else begin
            case (alu_asrc)
                1'b0: begin
                    alu_ia = r_data1;
                end
                1'b1: begin
                    alu_ia = inst_addr;
                end
            endcase
        end
    end


endmodule
